The present invention is related generally to a method and system for reducing power expenditure in an electronic device and, more particularly, to a method and system for providing a gated clock signal to a device which is disabled when not needed.
With the proliferation of buss connected devices, power consumption of electronic devices is becoming an increasing important design consideration. For example, devices operating on a universal serial bus (USB) may receive power from the USB bus. The USB bus provides approximately 0.5 amps of power through each port. Thus, relatively low power devices may be powered through the bus. Consequently, reducing power consumption of USB peripherals is an important design consideration.
USB peripheral designs generally consist of device logic and a set of registers, generally designates as a control and status register (CSR) block. As the name indicates, the set of registers include control registers and status registers. The control registers are typically programmed by an application outside the USB peripheral core. The control registers store different parameters required to implement core functionality of the USB peripheral.
The status registers store event information which occur on the USB bus, or cable. When an event occurs, one or more of the status registers are updated by the USB peripheral core. The application needs to read the status registers to get the updates. A clock signal is used to enable the application to both program and read the respective registers in the CSR block.
In current systems, the clock signal is unfortunately applied in a continuous manner to the CSR block, even though programming and reading of the registers accounts for only about 30 to 35 percent of the total time the USB peripheral is active. Accordingly, applying the clock signal to the CSR block in a continuous manner results in a waste of power. Although reducing power consumption is important to self powered devices, it is particularly important for bus powered devices.
Accordingly, there is a need in the art for a method and system for performing an operation, such as programming or reading, on a CSR block which reduces power consumption and which provides a clock signal to the CSR block substantially only when the CSR block is having an operation being performed thereon, such as programming or reading.
This need is met by a method and system in accordance with the present invention in which a gated clock signal is provided to a CSR block substantially only when an operation is being performed on the CSR block.
In accordance with one aspect of the present invention, a method for performing an operation by an application on a control and status register block is provided. The application detects when the operation, such as programming one or more control registers or reading one or more status registers, is needed. If the operation is to be performed, a gated clock signal is enabled to the control and status register. The application then performs the operation on the control and status register block based on the gated clock signal. Preferably, the gated clock signal is disabled after the operation has been performed.
In accordance with another aspect of the present invention, a method for reading a status register in an universal serial bus peripheral by an application comprises the steps of detecting when the status register has been updated and providing a gated clock signal to the status register in response to the update. The updated status register is then read by the application based on the gated clock signal. The gated clock signal may be disabled after the status register has been read.
In accordance with yet another aspect of the present invention, a method for programming a control register in an universal serial bus peripheral by an application is provided. First, it is detected when the control register needs to be programmed. When the control register needs to be programmed, a gated clock signal is provided to the control register. The control register is programmed by the application based on the gated clock signal. The gated clock signal may be disabled after the control register has been programmed by the application.
In accordance with a further aspect of the present invention, a system for performing an operation on a control and status register block in a universal serial bus peripheral is provided. Clock gating logic detects when the operation is to be performed and provides a gated clock signal to the control and status register block when the operation is to be performed. Application logic performs the operation on the control and status register block based on the gated clock signal.
The universal serial bus peripheral may generate an interrupt signal when the operation is to be performed. The clock gating logic may comprise an interrupt signal detection unit for detecting the interrupt signal and for enabling the gated clock signal in response to the interrupt signal. The operation may be reading of a status register in the control and status register block and/or programming a control register in the control and status register block. The application logic may comprise a status register read unit for reading the status register based on the gated clock signal. The application logic may comprise a control register program unit for programming a control register in the control and status register block based on the gated clock signal. The clock gating logic may disable the gated clock signal after the control register has been programmed.
In accordance with another aspect of the present invention, a gated clock logic which controls a gated clock signal which enable an operation to be performed on a control and status register block by an application is provided. The clock gating logic comprises a detection unit for detecting when the operation is to be performed. A gated clock signal enable unit provides the gated clock signal to the control and status register block when the operation is to be performed. The gated clock logic may include a gated clock signal disable circuit for disabling the gated clock signal when the operation is completed by the application.